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OKI Semiconductor ML2308
Stereo Recording/Playback LSI with Built-in Buffer Memory
PEDL2308DIGEST-03
Issue Date: Dec. 27, 2004
Preliminary
Both a serial interface and a parallel interface are available with the ML2308 through the use of a pin switch. Refer to pages 3 to 16 for information on the serial interface, and pages 17 to 24 for information on the parallel interface. Also, common information such as command functions, operation flow and examples of applied circuits are described on page 25 and subsequent pages.
GENERAL DESCRIPTION
The ML2308 is a stereo recording/playback LSI that has integrated in a single chip all the functions required for recording and playing back audio data. Analog signals fed into the microphone or line inputs are converted into digital signals by the analog to digital converter, and output to external equipment via the buffer memory. Further, digital signals from external equipment are converted into PWM signals by the 1-bit digital to analog converter, and output by the PWM driver that can directly drive the headphones. The influence of noise is lower with the ML2308 when compared with the mixed analog LSI, since most of the signals are digitally processed inside the LSI.
FEATURES
User Interfaces Supports Serial Peripheral Interface (SPI) or 8-bit bus interface Buffer memory for audio data buffer: 128 bytes (64 bytes each for left and right channels) Buffer memory status output pins FUL, MID, EMP Codec section/audio input and output sections Audio synthesis method: -law G.711compliant 8-bit PCM, 8-bit/16-bit linear PCM, 8-bit Oki non-linear PCM, 2-bit/3-bit/4-bit/5-bit/6-bit/7-bit/8-bit ADPCM2 Sampling frequency: 4.0 kHz to 32 kHz (selectable with commands) Built-in stereo - type 1-bit A/D converter S/(N+D): 80 dB DR, S/N: 85 dB Built-in stereo - type 1-bit D/A converter S/(N+D): 75 dB DR, S/N: 85 dB Built-in PWM driver for driving a speaker (150mW max, RL = 16, at BTL) Microphone amplifier x 2, Line amplifier x 2 (Stereo) Dynamic Range Control (DRC) automatic recording level adjustment function Recording input level detect function Control commands Volume control : 256 steps, 0 dB to -48.16 dB, OFF PAN control : 16 steps, 0 dB to -24.08 dB, OFF Power supply voltage Operating temperature Source oscillation frequency Package : +2.7 V to +3.6 V : -20C to +70C : 24.576MHz : 48-pin plastic QFN (P-VQFN48-0707-0.50) (ML2308GD)
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TABLE OF CONTENTS
General Description ........................................................................................................................... 1 Features .............................................................................................................................................. 1 (1) SERIAL INTERFACE ...................................................................................................................... 3 BLOCK DIAGRAM............................................................................................................................. 3 PIN CONFIGURATION (TOP VIEW) .............................................................................................. 4 description of Pins .............................................................................................................................. 5 When Placing an Order...................................................................................................................... 8 ABSOLUTE MAXIMUM RATINGS.................................................................................................. 9 RECOMMENDED OPERATING CONDITIONS............................................................................. 9 ELECTRICAL CHARACTERISTICS................................................................................................ 9 DC Characteristics.......................................................................................................................... 9 Analog Section Characteristics........................................................................................................ 10 Description of Functions ...................................................................................................................11 Command Interface .......................................................................................................................11 1. SPI mode.................................................................................................................................11 2. Command Data Write Timing .............................................................................................. 13 3. Status Read Timing .............................................................................................................. 13 Audio Interface.............................................................................................................................. 14 1. At I2S Formatting.................................................................................................................. 14 2. At Front-Aligned MSB First Formatting............................................................................. 15 3. Data Configurations for Respective Audio Synthesis Methods.......................................... 16 (2) Parallel Interface ............................................................................................................................ 17 Block diagram................................................................................................................................... 17 PIN CONFIGURATION (TOP VIEW) ............................................................................................ 18 Description of pins............................................................................................................................ 19 When Placing an Order.................................................................................................................... 22 ABSOLUTE MAXIMUM RATINGS................................................................................................ 23 RECOMMENDED OPERATING CONDITIONS........................................................................... 23 ELECTRICAL CHARACTERISTICS.............................................................................................. 23 DC Characteristics........................................................................................................................ 23 Analog Section Characteristics .................................................................................................... 24 (3) Common to Serial and parallel interfaces .................................................................................... 25 description of functions .................................................................................................................... 25 Relationship between Source oscillation frequency and Sampling Frequency......................... 25 Audio Synthesis Methods ............................................................................................................. 25 Restriction of Sampling Frequency ............................................................................................. 25 Buffer Memory Configuration...................................................................................................... 26 Command Functions ........................................................................................................................ 27 Command List............................................................................................................................... 27 Power Supply Wiring........................................................................................................................ 28 EXAMPLE Of APPLICATION CIRCUIT (when serial interface is used) .................................... 29 PACKAGE DIMENSIONS............................................................................................................... 30 Revision History ............................................................................................................................... 31
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(1) SERIAL INTERFACE BLOCK DIAGRAM
MOUTL MINLM MINLP LINL MOUTR MINRM MINRP LINR SG
-
+
-
+
ADC
AVDD Digital Filter Dynamic Range Controller AGND
-
+
SG
+
ADC
DVDD DGND
SERIAL CS SCK DI DO CBUSY VOX CPOL DIPH DOPH TEST EMP MID FUL
RESET
CPU I/F
PCM CODEC & -law CODEC
XT Oscillator XT
PVDD PGND RAM (64Byte x 2) OUTL OUTR
Digital Filter VOL & PAN
1bit DAC
PWM Driver
LR BCK DDI DDO
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PIN CONFIGURATION (TOP VIEW)
48-pin plastic VQFN (Serial interface)
FUL 1 MID 2 EMP 3 CPOL 4 DIPH 5 DOPH 6 DO 7 DI 8 SCK 9 CS 10 VOX 11 CBUSY 12 13 14 15 16 17 18 19 20 21 22 23 24 TEST XT XT TESTO0 LR BCK DDI DDO TESTO1 TESTO2 TESTO3 DGND
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 LINL AGND PGND OUTR OUTL PVDD DVDD SERIAL RESET TEST2 TEST1 TEST0
TESTO4 DGND DVDD AVDD MINRP MINRM MOUTR MINLP MINLM MOUTL LINR SG
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DESCRIPTION OF PINS
Command Interface Related Pins
Pin number 28 Pin name RESET I/O I Description The reset input pin. At "L" level input, the LSI is initialized. At that time, oscillation is stopped and the power is shut off. When turning the power on, input at the "L" level, and change to the "H" level once the supplied power voltage has been stabilized. The parallel/serial interface select pin. Fixed to "H" level when the serial interface is selected. The chip select input pin. At "L" level input, the command interface for the SCK, DI, and DO pins is enabled. It's unable to use CS pin fixed "L" level. CS pin should be "H" level after transferring 8bits command data. The command data input and status output serial clock input pin. The command data serial data input pin. The serial data output pin. The status signal in the LSI is output as a serial data, when a command is input subsequently following the input of the RDSTAT command. The pin to select the input pulse polarity of the SCK pin. When the CPOL pin is at the "L" level, the SCK will become "H" active. When the CPOL pin is at the "H" level, the SCK will become "L" active. The edge of the SCK pulse, at which data input at the DI pin is taken in the LSI, is selected with this pin. When the DIPH pin is at the "L" level, the data input at the DI pin is taken in the LSI at the rising edge of the SCK pulse. When the DIPH pin is at the "H" level, the data input at the DI pin is taken in the LSI at the falling edge of the SCK pulse. The edge of the SCK pulse, at which data is output to the DO pin, is selected with this pin. When the DOPH pin is at the "L" level, data is output to the DO pin at the falling edge of the SCK pulse. When the DOPH pin is at the "H" level, data is output to the DO pin at the rising edge of the SCK pulse. This pin outputs data at "L" level during command processing. Commands should be input with the CBUSY pin at the "H" level. The audio level detect signal output pin for recording. After recording has started, this pin outputs "H" once the recording input signal amplitude reaches the prescribed level.
29 10 9 8 7
SERIAL CS SCK DI DO
I I I I O
4
CPOL
I
5
DIPH
I
6
DOPH
I
12 11
CBUSY VOX
O O
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Audio Interface Related Pins
Pin number Pin name I/O Description This pin inputs the left or right side channel select signal for writing the audio data in the buffer memory or reading the audio data from the buffer memory. The outputs of the respective status signals in the buffer memory (EMP, MID and FUL) are switched by the input level of the LR pin input. Note that the status signal of the buffer memory is an output of a channel status signal that is opposite to that of the selected channel. [I2S format selected] When the LR pin is at the "L" level, access to the buffer memory of the left side will be permitted. The status signal of the buffer memory of the right side will be output. When the LR pin is at the "H" level, access to the buffer memory of the right side will be permitted. The status signal of the buffer memory of the left side will be output. [Front-aligned MSB first format selected] When the LR pin is at the "L" level, access to the buffer memory of the right side will be permitted. The status signal of the buffer memory of the left side will be output. When the LR pin is at the "H" level, access to the buffer memory of the left side will be permitted. The status signal of the buffer memory of the right side will be output. The serial clock input pin for buffer memory input and output. This is the pin for the input of serial data to the buffer memory. Data is taken into the LSI at the rising edge of the BCK clock. This is the pin for the output of serial data from the buffer memory. Data is output serially at the falling edge of the BCK clock. The status signal, indicating that the entire buffer memory is full of data, will be output. A "H" active or "L" active selection can be made with the OPT command. Recorded data after the buffer memory becomes full is not stored in the buffer memory and is discarded. Therefore, any data written after the buffer memory becomes full will not be played back. The status signal, indicating that at least half of the buffer memory is filled with data, will be output. A "H" active or "L" active selection can be made with the OPT command. Ordinarily, access to the buffer memory is controlled by the output of the MID pin. The status signal, indicating that there is no data in the entire buffer memory, will be output. A "H" active or "L" active selection can be made with the OPT command.
17
LR
I
18 19 20
BCK DDI DDO
I I O
1
FUL
O
2
MID
O
3
EMP
O
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Analog, Clock or Power Supply Related Pins
Pin number 39 40 41 42 43 44 36 38 37 33 Pin name MOUTL MINLM MINLP MOUTR MINRM MINRP LINL LINR SG OUTR I/O O I I O I I I I O O Description The output pin of the microphone amplifier on the left side. The inverted input pin of the microphone amplifier on the left side. The non-inverted input pin of the microphone amplifier on the left side. The output pin of the microphone amplifier on the right side. The inverted input pin of the microphone amplifier on the right side. The non-inverted input pin of the microphone amplifier on the right side. The input pin of the line amplifier on the left side. The input pin of the line amplifier on the right side. The output pin for the reference voltage (signal ground) of the analog circuit. The playback output pin for the right side. An external LC filter has been configured to eliminate a high-frequency component, as the PWM pulse is output. The playback output pin for the left side. An external LC filter has been configured to eliminate a high-frequency component, as the PWM pulse is output. An oscillator connection pin. When using an external clock, input it from this pin. An oscillator connection pin. When using an external clock, leave this open. Test pins. Keep these pins "L" level, as these pins don't have pull-up resistors. A test pin. Fix it at "L". It has a built-in pull-down resistor Test pins. Leave them open when the circuit board is connected. The digital power supply pins. Connect a bypass capacitor of 0.1F or more between these pins and the DGND pin. The digital ground pins. The analog power supply pin. Connect a bypass capacitor of 0.1F or more between this pin and the AGND pin. The analog ground pin. The power supply pin for the PWM driver. Connect a bypass capacitor of 10F or more between this pin and the PGND pin. The ground pin for the PWM driver.
32 14 15 25,26,27 13 16,21,22, 23,48 30,46 24,47 45 35 31 34
OUTL XT XT TEST2-0 TEST TESTO4-0 DVDD DGND AVDD AGND PVDD PGND
O I O I I O
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WHEN PLACING AN ORDER
Specify ML2308GD (Package: 48-pin plastic VQFN).
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ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Power Dissipation Output short current Storage temperature Symbol VDD VIN PD ISC TSTG Condition Ta = 25C Ta = 25C Ta = 25C(Note 1) Ta = 25C(Note 2) -- Rating -0.3 to +5.0 -0.3 to VDD + 0.3 890 10 100 -55 to +150 Unit V V mW mA mA C
Notes:
1. Applies to output pins excluding OUTL and OUTR pins. 2. Applies to OUTL and OUTR pins.
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Operating temperature Source clock frequency Symbol VDD Top fOSC Condition DGND = AGND = 0 V -- -- Range 2.7 to 3.6 -20 to +70 20 to 25 Unit V C MHz
ELECTRICAL CHARACTERISTICS
DC Characteristics
DVDD = AVDD = 2.7 to 3.6 V DGND = AGND = 0 V, Ta = -20 to +70C Min. Typ. Max. Unit VDD x 0.8 VDD +0.3 V -0.3 0.6 V VDD - 0.4 V 0.4 V 10 A 0.3 20 A 30 180 A -10 A -20 -0.3 A 30 40 20 100 mA A A
Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current (Note 1) "H" input current (Note 2) "H" input current (Note 3) "H" input current (Note 4) "L" input current (Note 2) Operating current consumption Current consumption during power down
Symbol VIH VIL VOH VOL IIH1 IIH2 IIH3 IIL1 IIL2 IDD IDDS
Condition IOH = -1 mA IOL = 2 mA VIH = VDD VIH = VDD VIH = VDD VIL = GND VIL = GND fOSC = 24.576 MHz at no load Ta = -20 to +50C Ta = +50 to +70C
Notes:
1. Applies to input pins excluding XT and TEST pins. 2. Applies to XT pin. 3. Applies to TEST pin. 4. Applies to input pins excluding XT pin.
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Analog Section Characteristics
DVDD = AVDD = 2.7 to 3.6 V DGND = AGND = 0 V, Ta = -20 to +70C Min. Typ. Max. Unit 1 -- -- M 22 -- 100 -- 0.48 x VDD 12 -- 32 -- -- -- 0.5 x VDD 15 -- 42 0.6 x VDD -- 30 0.52 x VDD 18 150 k Vpp k dB V k mW
Parameter MIN input impedance LINL, LINR input impedance LIN1, LIN2 input amplitude MOUT, LOUTL, LOUTR output load resistance Microphone amplifier gain setting range SG output voltage SG output resistance OUTL, OUTR output power
Symbol RINM RINL VLIN ROUTA GMIC VSG RSG POUT
Condition -- When line input is used -- -- -- -- -- At BTL output RL = 16 S/(N+D)> -20dB =
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DESCRIPTION OF FUNCTIONS
Command Interface 1. SPI mode The ML2308 supports eight types of SPI modes as available command interface modes. These SPI modes can be selected with the CPOL pin, DIPH pin and DOPH pin. Fix the output level to "L" or "H" as the SPI mode setting cannot be changed once the power has been turned on. Setting descriptions for the CPOL pin, DIPH pin and DOPH pin are shown below:
Pin CPOL DIPH DOPH Input Level "L" level "H" level "L" level "H" level "L" level "H" level Setting descriptions "H" pulse is input as the SCK pulse. "L" pulse is input as the SCK pulse. The input data of the DI pin is taken in at the rising edge of the SCK pulse. The input data of the DI pin is taken in at the falling edge of the SCK pulse. Data is output to the DO pin at the falling edge of the SCK pulse. Data is output to the DO pin at the rising edge of the SCK pulse.
Timing diagrams of respective SPI modes are shown below: * CPOL = "L", DIPH = "L", DOPH = "L"
CS (I) SCK (I) DI (I) DO(O) CBUSY (O)
* CPOL = "L", DIPH = "L", DOPH = "H"
D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7
CS (I) SCK (I) DI (I) DO(O) D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7
* CPOL = "L", DIPH = "H", DOPH = "L"
CS (I) SCK (I) DI (I) DO(O) D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7
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* CPOL = "L", DIPH = "H", DOPH = "H"
CS (I) SCK (I) DI (I) DO(O) D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7
* CPOL = "H", DIPH = "L", DOPH = "L"
CS (I) SCK (I) DI (I) DO(O) D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7
* CPOL = "H", DIPH = "L", DOPH = "H"
CS (I) SCK (I) DI (I) DO(O) D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7
* CPOL = "H", DIPH = "H", DOPH = "L"
CS (I) SCK (I) DI (I) DO(O) D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7
* CPOL = "H", DIPH = "H", DOPH = "H"
CS (I) SCK (I) DI (I) DO(O) D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7
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2. Command Data Write Timing The timing for writing command data is shown below. After "L" is input to the CS pin, 8-bit command data is input to the DI pin serially from the LSB, synchronized with the input clock signal of the SCK pin. After 8 SCK clock signals have been input, "L" is output to the CBUSY pin. While the CBUSY pin is "L", the serial interface cannot be used. It waits for the CBUSY pin output to become "H" before inputting the next command data. Please change CS pin to "H" level after one command inputted. A timing diagram for the case where the CPOL pin is set at the "H" level and the DIPH pin is set at "L" level is shown below. The "L" level output time of the CBUSY pin, tCBSY, varies depending on the operating state of the LSI.
CS (I) SCK (I) DI (I) CBUSY (O)
tCBSY
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2
3. Status Read Timing The timing for reading status signals is shown below. After "L" is input to the CS pin and the status read command (RDSTAT command) is input, 8-bit status data is output to the DO pin serially from the LSB synchronized with the falling edge of the input clock signal of the SCK pin. A timing diagram for the case where the CPOL pin is set at the "H" level, the DIPH pin at "L" level, and the "DOPH" at the "L" level is shown below.
CS (I) SCK (I) DI (I) DO (O) CBUSY (O)
tCBSY tCBSY Hi-Z
RDSTAT COMMAND
O0 O1 O2 O3 O4 O5 O6 O7
Hi-Z
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Audio Interface The audio interface is used to write the audio data into and read the audio data out of the buffer memory during recording and playback. As an audio interface, the ML2308 supports two types of interface formats (I2S format and front-aligned MSB first format). Access to the buffer memory is made from the LR pin, BCK pin, DDI pin and DDO pin regardless of the selected format. 1. At I2S Formatting Access timing to the buffer memory with the I2S format is shown below:
LR (I) BCK (I) DDI (I) DDO (O) D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 Left Right Left
O15 O14 O13 O2 O1 O0 O15 O14 O13 O2 O1 O0 O15 O14 Left Data Right Data
During playback, the 16-bit playback data is input serially from the MSB to the DDI pin in synchronization with the clock signal of the BCK pin. The DDI pin input data is taken in the LSI at the rising edge of the BCK clock signal. The recording data is output from the DDO pin at the falling edge of the BCK clock signal during recording. The left side data is input and output when the level of the LR pin is at "L" and the right side data is input and output when the level of the LR pin is at "H". The status signal output (EMP, MID and FUL) of the buffer memory is also switched according to the input level of the LR pin. The right side status data is output when the level of the LR pin is at "L" and the left side status signal is output when the level is at "H". Note that the status of the opposite chanel is output when compared with the input and output of the data. When the buffer memory is empty, the read data will be 0000h (hexadecimal) if reading is performed. If the BCK clock signal is input for the duration of 16 clocks or more while the LR pin is at "H" or "L", then the 16-bit front-aligned data will become valid data. The buffer memory access timing, when the BCK clock is 16-bit or more, is shown below:
LR (I) BCK (I) DDI (I) DDO (O)
MSB MSB LSB LSB MSB MSB LSB LSB MSB MSB
Left
Right
Left
Left 16bit Data
Right 16bit Data
It is necessary to access both the left and right sides of the buffer memory during monaural recording and playback as well. Since buffer memory access of an unused channel will be ignored, there will be no effect to the channels that are in use. The status signal of an unused channel retains the empty state, even for the status signals of the buffer meory (EMP, MID and FUL) as well. For example, when recording with the left side channel, the audio data read from the right side channel will be 0000h (hexadecimal). When playing back, the values written in the right side of the buffer memroy will be ignored.
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2. At Front-Aligned MSB First Formatting The buffer memory access timing for the front-aligned MSB first format is shown below:
LR (I) BCK (I) DDI (I) DDO (O) D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 Left Right Left
O15 O14 O13 O2 O1 O0 O15 O14 O13 O2 O1 O0 O15 O14 Left Data Right Data
During playback, the 16-bit playback data is input serially from the MSB to the DDI pin in synchronization with the clock signal of the BCK pin. The DDI pin input data is taken in the LSI at the rising edge of the BCK clock signal. The recording data is output from the DDO pin at the falling edge of the BCK clock signal during recording. The left side data is input and output when the level of the LR pin is at "H" and the right side data is input and output when the level of the LR pin is at "L". The status signal output (EMP, MID and FUL) of the buffer memory is also switched according to the input level of the LR pin. The right side status data is output when the level of the LR pin is at "H" and the left side status signal is output when the level is at "L". Note that the status of the opposite chanel is output when compared with the input and output of the data. When the buffer memory is empty, the read data will be 0000h (hexadecimal) if reading is performed. If the BCK clock signal is input for the duration of 16 clocks or more while the LR pin is at "H" or "L", then the 16-bit front-aligned data will become valid data. The buffer memory access timing, when the BCK clock is 16-bit or more, is shown below:
LR (I) BCK (I) DDI (I) DDO (O)
MSB MSB LSB LSB MSB MSB LSB LSB MSB MSB
Left
Right
Left
Left 16bit Data
Right 16bit Data
It is necessary to access both the left and right sides of the buffer memory during monaural recording and playback as well. Since buffer memory access of an unused channel will be ignored, there will be no effect to the channels that are in use. The status signal of an unused channel retains the empty state, even for the status signals of the buffer meory (EMP, MID and FUL) as well. For example, when recording with the left side channel, the audio data read from the right side channel will be 0000h (hexadecimal). When playing back, the values written in the right side of the buffer memroy will be ignored.
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3. Data Configurations for Respective Audio Synthesis Methods The configuration of the audio data that is input to and output from the buffer memory during recording and playback, for each respective audio synthesis method, is shown in the table below: 1) 2-bit ADPCM2 method
D15 MSB1 D7 MSB5 D14 LSB1 D6 LSB5 D13 MSB2 D5 MSB6 D12 LSB2 D4 LSB6 D11 MSB3 D3 MSB7 D10 LSB3 D2 LSB7 D9 MSB4 D1 MSB8 D8 LSB4 D0 LSB8
2) 3-bit ADPCM2 method
D15 0 D7 2SB3 D14 MSB1 D6 LSB3 D13 2SB1 D5 MSB4 D12 LSB1 D4 2SB4 D11 MSB2 D3 LSB4 D10 2SB2 D2 MSB5 D9 LSB2 D1 2SB5 D8 MSB3 D0 LSB5
3) 4-bit ADPCM2 method
D15 MSB1 D7 MSB3 D14 3SB1 D6 3SB3 D13 2SB1 D5 2SB3 D12 LSB1 D4 LSB3 D11 MSB2 D3 MSB4 D10 3SB2 D2 3SB4 D9 2SB2 D1 2SB4 D8 LSB2 D0 LSB4
4) 5-bit ADPCM2 method
D15 0 D7 3SB2 D14 MSB1 D6 2SB2 D13 4SB1 D5 LSB2 D12 3SB1 D4 MSB3 D11 2SB1 D3 4SB3 D10 LSB1 D2 3SB3 D9 MSB2 D1 2SB3 D8 4SB2 D0 LSB3
5) 6-bit ADPCM2 method
D15 0 D7 2SB1 D14 0 D6 LSB1 D13 0 D5 MSB2 D12 0 D4 5SB2 D11 MSB1 D3 4SB2 D10 5SB1 D2 3SB2 D9 4SB1 D1 2SB2 D8 3SB1 D0 LSB2
6) 7-bit ADPCM2 method
D15 0 D7 LSB1 D14 0 D6 MSB2 D13 MSB1 D5 6SB2 D12 6SB1 D4 5SB2 D11 5SB1 D3 4SB2 D10 4SB1 D2 3SB2 D9 3SB1 D1 2SB2 D8 2SB1 D0 LSB2
7) 8-bit ADPCM2, 8-bit straight PCM, 8-bit non-linear PCM, or -law PCM method
D15 MSB1 D7 MSB2 D14 7SB1 D6 7SB2 D13 6SB1 D5 6SB2 D12 5SB1 D4 5SB2 D11 4SB1 D3 4SB2 D10 3SB1 D2 3SB2 D9 2SB1 D1 2SB2 D8 LSB1 D0 LSB2
8) 16-bit straight PCM method
D15 MSB1 D7 8SB1 D14 15SB1 D6 7SB1 D13 14SB1 D5 6SB1 D12 13SB1 D4 5SB1 D11 12SB1 D3 4SB1 D10 11SB1 D2 3SB1 D9 10SB1 D1 2SB1 D8 9SB1 D0 LSB1
This concludes the descriptions on the serial interface. Refer to Section (3) for details concerning common items, such as command lists, operation flows and examples of applied circuits.
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(2) PARALLEL INTERFACE BLOCK DIAGRAM
MOUTL MINLM MINLP LINL MOUTR MINRM MINRP LINR SG SERIAL TEST CBUSY VOX CS WR RD D/C CH D7-D0 CPU I/F
+
+
ADC
Digital Filter Dynamic Range Controller
AVDD AGND
+
+ SG
ADC
DVDD DGND
RESET
PCM CODEC & -law CODEC
XT Oscillator XT
PVDD PGND OUTL OUTR
EMP MID FUL
RAM (64Byte x 2)
Digital Filter VOL & PAN
1bit DAC
PWM Driver
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PIN CONFIGURATION (TOP VIEW)
48-pin plastic VQFN (Parallel interface)
FUL 1 MID 2 EMP 3 RD 4 WR 5 CH 6 TESTO0 7 TESTO1 8 D/C 9 CS 10 VOX 11 CBUSY 12 TEST XT XT D0 D1 D2 D3 D4 D5 D6 D7 DGND 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 LINL AGND PGND OUTR OUTL PVDD DVDD SERIAL RESET TEST2 TEST1 TEST0
TESTO2 DGND DVDD AVDD MINRP MINRM MOUTR MINLP MINLM MOUTL LINR SG
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DESCRIPTION OF PINS
Command Interface Related Pins
Pin number 28 Pin name RESET I/O I Description The reset input pin. At "L" level input, the LSI is initialized. At that time, oscillation is stopped and the power is shut off. When turning the power on, input at the "L" level, and change to the "H" level once the supplied power voltage has been stabilized. The CPU interface select pin. The level is fixed to "L" when the parallel interface is selected. The select input pin for the command interface and the audio interface. The WR and RD inputs are accepted at the "L" level. The WR and RD signal inputs are ignored at the "H" level. The select input pin for the command interface and the audio interface. The level of the D/C pin is set to "L" and the "L" pulse is input to the WR and RD pins when inputting a command or outputting the internal status. The audio interface becomes enabled when the level is at "H". The write pulse input pin. This pin is used in common by the command interface and the audio interface. [The "L" level selected for the D/C pin] The input data of the D7 to D0 pins is taken into the LSI as command data at the rising edge of the WR pin. Once the command data is taken in, the "L" level is output to the CBUSY pin, indicating that a command process is taking place. A "L" level command input of the CBUSY pin will be ignored. The command is input while the level of the CBUSY pin is at "H". [The "H" level selected for the D/C pin] Refer to the descriptions on the audio interface related pins on the next page. The read pulse input pin. This pin is used in common by the command interface and the audio interface. [The "L" level selected for the D/C pin] Status data is output to the D7 to D0 pins while the level of the RD pin is at "L". In order to read the internal status, the level of the RD pin is set to "L" after the input of the RDSTAT command. Note that the status data will not be updated unless the RDSTAT command has been input. [The "H" level selected for the D/C pin] Refer to the descriptions on the audio interface related pins on the next page. Data is input or output with the bi-directional data bus. These pins are used in common by the command interface and the audio interface. This pin outputs data at "L" level during command processing. Commands can be input when the CBUSY pin is at the "H" level. The audio level detect signal output pin for recording. After recording has started, this pin outputs "H" once the recording input signal amplitude reaches the prescribed level.
29 10
SERIAL CS
I I
9
D/C
I
5
WR
I
4
RD
I
16-23 12 11
D7-D0 CBUSY VOX
I/O O O
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ML2308
Audio Interface Related Pins
Pin number 10 Pin name CS I/O I Description The select input pin for the command interface and the audio interface. The WR and RD inputs are accepted when set to the "L" level. The WR and RD signal inputs are ignored when set to the "H" level. The select input pin for the command interface and the audio interface. When the audio data is input or output, the level of the D/C pin is set to "H" and the "L" level pulse is input to the WR and RD pins. The command interface is enabled when the level is at "L". The select input pin for the audio interface channel. When the level is at "L", the buffer memory of the left side is selected and the buffer memory status of the left side is output as status output of the EMP, MID and FUL pins. When the level is at "H", the buffer memory of the right side is selected and the buffer memory status of the right side is output as status output of the EMP, MID and FUL pins. The write pulse input pin. This pin is used in common by the command interface and the audio interface. [The "H" level selected for the D/C pin] The input data of the D7 to D0 pins are written into the buffer memory, which has been selected with the CH pin, at the rising edge of the WR pin. The state of the CS pin is irrelevant. [The "L" level selected for the D/C pin] Refer to the descriptions on the command interface related pins on the preceding page. The read pulse input pin. This pin is used in common by the command interface and the audio interface.
9
D/C
I
6
CH
I
5
WR
I
4
RD
I
16-23
D7-D0
I/O
1
FUL
O
2
MID
O
3
EMP
O
[The "H" level selected for the D/C pin] While the level of the RD pin is at "L", the data read from the buffer memory, which has been selected with the CH pin, is output to the D7 to D0 pins. [The "L" level selected for the D/C pin] Refer to the descriptions on the command interface related pins on the preceding page. Data is input or output with the bi-directional data bus. These pins are used in common by the command interface and the audio interface. The status signal, indicating that the entire buffer memory is full of data, will be output. A "H" active or "L" active selection can be made with the OPT command. Recordings made after the buffer memory becomes full are not stored in the buffer memory and are discarded. Therefore, any data written after the buffer memory becomes full, will not be played back. The status signal, indicating that at least half of the buffer memory is filled with data, will be output. A "H" active or "L" active selection can be made with the OPT command. Ordinarily, access to the buffer memory is controlled by the output of the MID pin. The status signal, indicating that there is no data in the entire buffer memory, will be output. A "H" active or "L" active selection can be made with the OPT command.
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ML2308
Analog, Clock or Power Supply Related Pins
Pin number 39 40 41 42 43 44 36 38 37 33 Pin name MOUTL MINLM MINLP MOUTR MINRM MINRP LINL LINR SG OUTR I/O O I I O I I I I O O Description The output pin of the microphone amplifier on the left side. The inverted input pin of the microphone amplifier on the left side. The non-inverted input pin of the microphone amplifier on the left side. The output pin of the microphone amplifier on the right side. The inverted input pin of the microphone amplifier on the right side. The non-inverted input pin of the microphone amplifier on the right side. The input pin of the line amplifier on the left side. The input pin of the line amplifier on the right side. The output pin for the reference voltage (signal ground) of the analog circuit. This is the playback output pin for the right side. An external LC filter has been configured to eliminate a high-frequency component, as the PWM pulse is output. This is the playback output pin for the left side. An external LC filter has been configured to eliminate a high-frequency component, as the PWM pulse is output. An oscillator connection pin. When using an external clock, input it from this pin. An oscillator connection pin. When using an external clock, leave this open. Test pins. Keep these pins "L" level, as these pins don't have pull-up resistors. A test pin. Fix it at "L". It has a built-in pull-down resistor Test pins. Leave them open when the circuit board is connected. The digital power supply pins. Connect a bypass capacitor of 0.1F or more between these pins and the DGND pin. The digital ground pins. The analog power supply pin. Connect a bypass capacitor of 0.1F or more between this pin and the AGND pin. The ground supply pin. The power supply pin for the PWM driver. Connect a bypass capacitor of 10F or more between this pin and the PGND pin. The ground pin for the PWM driver.
32 14 15 25, 26, 27 13 7, 8, 48 30, 46 24, 47 45 35 31 34
OUTL XT XT TEST2-0 TEST TESTO2-0 DVDD DGND AVDD AGND PVDD PGND
O I O I I O
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WHEN PLACING AN ORDER
Specify ML2308GD (Package: 48-pin plastic VQFN).
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ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Power Dissipation Output short current Storage temperature Symbol VDD VIN PD ISC TSTG Condition Ta = 25C -- Ta = 25C Ta = 25C(Note 1) Ta = 25C(Note 2) -- Rating -0.3 to +5.0 -0.3 to VDD + 0.3 890 10 100 -55 to +150 Unit V V mW mA mA C
Notes:
1. Applies to output pins excluding OUTL and OUTR pins. 2. Applies to OUTL and OUTR pins.
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Operating temperature Source clock frequency Symbol VDD Top fOSC Condition DGND = AGND = 0 V -- -- Range 2.7 to 3.6 -20 to +70 20 to 25 Unit V C MHz
ELECTRICAL CHARACTERISTICS
DC Characteristics
DVDD = AVDD = 2.7 to 3.6 V DGND = AGND = 0 V, Ta = -20 to +70C Min. Typ. Max. Unit VDD x 0.8 VDD +0.3 V -0.3 0.6 V VDD - 0.4 V 0.4 V 10 A 0.3 30 -10 -20 30 20 150 -0.3 40 20 100 A A A A mA A A
Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current (Note 1) "H" input current (Note 2) "H" input current (Note 3) "H" input current (Note 4) "L" input current (Note 2) Operating current consumption Current consumption during power down
Symbol VIH VIL VOH VOL IIH1 IIH2 IIH3 IIL1 IIL2 IDD IDDS
Condition IOH = -1 mA IOL = 2 mA VIH = VDD VIH = VDD VIH = VDD VIL = GND VIL = GND fOSC = 24.576 MHz at no load Ta = -20 to +50C Ta = +50 to +70C
Notes:
1. Applies to input pins excluding XT and TEST pins. 2. Applies to XT pin. 3. Applies to TEST pin. 4. Applies to input pins excluding XT pin.
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Analog Section Characteristics
DVDD = AVDD = 2.7 to 3.6 V DGND = AGND = 0 V, Ta = -20 to +70C Min. Typ. Max. Unit 1 M 22 100 0.48 x VDD 12 32 0.6 x VDD 0.5 x VDD 15 42 30 0.52 x VDD 18 150 k Vpp k dB V k mW
Parameter MIN input impedance LINL, LINR input impedance LIN1, LIN2 maximum input amplitude MOUT, LOUTL, LOUTR output load resistance Microphone amplifier gain setting range SG output voltage SG output resistance OUTL, OUTR output power
Symbol RINM RINL VLIN ROUTA GMIC VSG RSG POUT
Condition When line input is used At BTL output RL = 16 S/(N+D)> -20dB =
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(3) COMMON TO SERIAL AND PARALLEL INTERFACES DESCRIPTION OF FUNCTIONS
Relationship between Source oscillation frequency and Sampling Frequency The sampling frequency fSAM is selected with the S3 to S0 bits of the METHOD command. Respective sampling frequencies are determined by the relational expression with the source oscillation frequency fOSC, as shown below:
S3 0 0 0 0 0 1 1 1 1 1 S2 0 1 1 1 1 0 0 0 0 1 S1 X 0 0 1 1 0 0 1 1 X S0 X 0 1 0 1 0 1 0 1 X Relationship between fSAM and fOSC fSAM=fOSC/6144 fSAM=fOSC/3072 fSAM=fOSC/1536 fSAM=fOSC/768 fSAM=fOSC/4096 fSAM=fOSC/2048 fSAM=fOSC/1024 Sampling Frequency when fOSC = 24.576MHz Not used 4.0kHz 8.0kHz 16.0kHz 32.0kHz 6.0kHz 12.0kHz 24.0kHz Not used Not used
Note: X means "Don't care".
Audio Synthesis Methods This LSI supports four types of audio synthesis methods to meet the needs of various audio types: 2-bit/3-bit/4-bit/5-bit/6-bit/7-bit/8-bit ADPCM2, 8-bit/16-bit straight PCM, 8-bit nonlinear PCM and -law PCM. 2-bit/3-bit/4-bit/5-bit/6-bit/7-bit/8-bit ADPCM2 The ADPCM2 method is an audio synthesis method that achieves higher sound quality than ADPCM (Adaptive Differential Pulse Code Modulation). This method adaptively changes the quantized width for each sample and codes it as 2-bit to 8-bit data. For human voices, animal cries, or natural sounds, this method allows the audio data volume to be reduced. 8-bit/16-bit Straight PCM This method is the best of the three methods for following audio waveforms in all audio areas. It is suitable for sounds with sudden waveform changes and waveforms in pulse forms. 8-bit Nonlinear PCM This method is for playing back audio input in the range of 7/16 VDD to 9/16 VDD as 10-bit straight PCM sound quality, and for improving the sound quality of waveforms with low amplitude. -law PCM This method is for G.711 compliant playback.
Restriction of Sampling Frequency To record and playback by ADPCM2 method, please set the sampling frequency under 16 kHz. Noise will happen because data does not be processed normally,if the sampling frequency is set 24kHz. In addition, all sampling frequency can be used on all PCM methods.
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Buffer Memory Configuration There are two buffer memories, one for the left side and the other for the right side. The capacity of the buffer memory can be selected with the OPT command from among 512 bits, 256 bits and 128 bits. However, the memory capacity that varies from one channel to another cannot be set. Since the buffer time varies depending on the audio synthesis method and sampling frequency used, select the buffer memory capacity in proportion to the load of the CPU for the external control. The default value is set to 512 bits. The maximum buffer time for the buffer memory of respective audio synthesis methods, with the buffer memory capacity of 512 bits and sampling frequency of 16kHz, is shown below:
Audio Synthesis Method 2-bit ADPCM2 3-bit ADPCM2 4-bit ADPCM2 5/6/7/8-bit ADPCM2 8-bit straight PCM 8-bit non-linear PCM 8-bit -law PCM 16-bit straight PCM Maximum Buffer Time 256 samples/16kHz = 16 ms 160 samples/16kHz = 10 ms 128 samples/16kHz = 8 ms 64 samples/16kHz = 4 ms 32 samples/16kHz = 2 ms
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COMMAND FUNCTIONS
Command List
Command name NOOP PDWN REC PLAY STOP PAUSE BPLAY NOOP METHOD VOL PAN DRC ATLT RDSTAT OPT MTSPD OPTANA D7 0 0 0 0 0 0 0 0 0 1 P3 1 V7 1 R3 1 0 1 LT3 1 1 0 1 1 OP7 D6 0 0 0 0 1 1 1 0 1 0 P2 0 V6 0 R2 0 0 1 LT2 1 1 0 1 1 OP6 D5 0 0 1 1 0 0 1 0 1 0 P1 0 V5 1 R1 1 0 0 LT1 0 1 0 1 1 OP5 D4 0 1 0 1 0 1 0 0 1 0 P0 1 V4 0 R0 1 DR4 0 LT0 1 0 ADT 0 1 OP4 D3 0 0 0 0 0 0 0 0 0 0 S3 0 V3 0 L3 0 DR3 0 AT3 0 0 AI 1 0 OP3 D2 0 0 0 0 0 CL 0 B2 0 0 S2 0 V2 0 L2 0 DR2 0 AT2 0 0 M1 0 0 OP2 D1 0 0 R R R R R B1 0 R S1 R V1 R L1 0 DR1 0 AT1 0 0 M0 MS1 0 OP1 D0 0 1 L L L L L B0 0 L S0 L V0 L L0 0 DR0 0 AT0 0 0 A MS0 0 OP0 Function No function Power down command Recording start command Playback start command Recording/playback stop command Recording/playback pause command Block playback start command No function Audio synthesis method, sampling frequency setting command Volume setting command Panpot setting command Automatic level control setting command ADC attack time/release time setting command Status read command Buffer memory capacity/pin status/stereo/buffer memory serial interface setting Transition time setting command when varying volume Analog option setting command
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POWER SUPPLY WIRING
The power supply of the ML2308 is divided into the following three supplies * Digital power supply (DVDD) * Analog power supply for analog circuits (AVDD) * Analog power supply for audio output driver (PVDD) Supply DVDD, PVDD, and AVDD from the same power supply and divide the wiring for the analog and digital systems as shown below.
ML2308
DVDD DGND
3V
PVDD AVDD
PGND AGND
Do not arrange the wiring as shown below.
Analog power supply Digital power supply Power supply DVDD DVDD AVDD PVDD AVDD PVDD
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EXAMPLE OF APPLICATION CIRCUIT (WHEN SERIAL INTERFACE IS USED)
+3V
0.1F 0.1F
DVDD MCU RESET CS SCK DI DO CBUSY EMP MID FUL LR BCK DDI DDO CPOL DIPH DOPH TEST2 TEST1 TEST0 TEST
AVDD PVDD
10F
220F
100H
OUTL
0.22F 1k
Headphone Jack
220F
100H 0.22F
OUTR
1k
ML2308
LINL LINR
LINE-IN1 0.1F LINE-IN2 0.1F 20k 0.1F 2k
MINLP MINLM MOUTL
20k 200k 10k 0.1F 20k 2k ECM
XT
24.567MHz
0.1F
MINRP MINRM MOUTR
20k 200k 10k 0.1F ECM
XT
5pF
5pF
DGND
AGND PGND
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PACKAGE DIMENSIONS
(Unit: mm)
P-VQFN48-0707-0.50-1
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Lead finish Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin Cu alloy Sn/Pb=70/30 to 95/5 Solder plating ( 5m) 0.095 TYP. 1/May 20, 2003
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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REVISION HISTORY
Page Document No. PEDL2308DIGEST-01 PEDL2308DIGEST-02 PEDL2308DIGEST-03 Date Aug. 9, 2004 Dec.14,2004 Dec.27,2004 Previous Edition - - - Current Edition - - - Description Preliminary edition 1 Preliminary edition 2 Preliminary edition 3
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd.
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